Mixed technology integrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage

ABSTRACT

Complementary LDMOS and MOS structures and vertical PNP transistors capable of withstanding a relatively high voltage may be realized in a mixed-technology integrated circuit of the so-called “smart power” type, by forming a phosphorus doped n-region of a similar diffusion profile, respectively in: The drain zone of the n-channel LDMOS transistors, in the body zone of the p-channel LDMOS transistors forming first CMOS structures; in the drain zone of n-channel MOS transistors belonging to second CMOS structures and in a base region near the emitter region of isolated collector, vertical PNP transistors, thus simultaneously achieving the result of increasing the voltage withstanding ability of all these monolithically integrated structures. The complementary LDMOS structures may be used either as power structures having a reduced conduction resistance or may be used for realizing CMOS stages capable of operating at a relatively high voltage (of about 20V) thus permitting a direct interfacing with VDMOS power devices without requiring any “level shifting” stages. The whole integrated circuit has less interfacing problems and improved electrical and reliability characteristics.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.08/625,974, filed Apr. 1, 1996, now abandoned; which is a continuationof U.S. patent application Ser. No. 08/083,277, filed Jun. 28, 1993, nowabandoned; which is a reissue application of U.S. patent applicationSer. No. 07/535,774, filed Jun. 8, 1990, U.S. Pat. No. 5,041,895.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a mixed technology, “smart power”,integrated device containing power transistors and control logic andanalog driving circuitry combined in a monolithic silicon chip.

2. Description of the Prior Art

The commercial success of so-called “smart power” integrated circuits,wherein the analog signal processing circuitry, the control logiccircuitry and the output power devices are conveniently monolithicallyintegrated in a single chip, originated and sprung from the overcomingof compatibility problems among the different fabrication processesrelative to the different integrated devices, often necessarilyoperating under different supply voltages. Most often, even thoughnon-exclusively, the power section of such integrated circuits employsVDMOS transistors which typically require a driving gate voltage levelcomprised between about 10 V-20 V.

This makes difficult interfacing the power transistor (e.g. VDMOS) withthe driving circuitry. Commonly, in fact, the maximum operating voltageof CMOS transistors used in logic circuitry is 5 V. Conversely, thedriving circuitry for power transistors operate at about 12 V, while inorder to ensure a driving level on the gate of a VDMOS power transistorof 10 V and if a reasonable process “spread” is accounted for, thesupply voltage of CMOS transistors of the relative driving circuitshould be at least 15 V. Moreover better operating conditions of a VDMOSpower transistor (i.e. a lower resistance R_(on)) may be achieved if thedriving voltage level on the gate may be raised to 15-20 V, as it iswell known to a skilled technician.

In “smart power” type integrated circuits, this particular problem iscommonly obviated by using a “level shifter” circuit, which necessarilymakes the driving circuit more complicated.

There is a definite need for the availability of CMOS transistors havingan operating voltage of about 20 V in a monolithically integratedsemiconductor device of the “smart power” type in order to drivedirectly the output power transistors with a relatively high voltagewithout employing special level shifter circuits.

On the other hand, in these integrated circuits there are other CMOS andbipolar transistors which are employed, because of their peculiarcharacteristics, in control logic circuitry and in signal processingcircuitry, respectively. Also the utility and reliability of these otherintegrated devices could be advantageously enhanced if also these otherintegrated devices could be made capable of withstanding a higher supplyvoltage than the voltage normally allowed by the physical structure ofthese integrated devices produced through a mixed-technology fabricationprocess.

OBJECTIVE AND SUMMARY OF THE INVENTION

In view of this state of the art, the present invention has the mainobjective of providing, in a monolithically integrated “smart power”type device, CMOS structures and isolated collector, vertical, PNPtransistors capable of withstanding a higher operating voltage than thevoltage normally withstood by these devices, when they are formedmonolithically together in a single chip.

This objective is reached by the integrated device of the invention, asdefined in the annexed claims.

Structurally the device is characterized by the fact that it comprisesregions of phosphorus doped, n-type silicon of similar diffusion profileextending from the surface of the n-type epitaxial layer wherein thedifferent devices are formed, respectively, through the drain area ofn-channel LDMOS transistors extending between the gate electrode thereofand the adjacent isolating field oxide, the body area of p-channel LDMOStransistors, extending between the gate electrode thereof and theadjacent isolation field oxide, the drain area of n-channel MOStransistors, extending between the gate electrode thereof and theadjacent isolation field oxide, and the emitter area of isolatedcollector vertical PNP bipolar transistors, and by a depth sufficient tocontain, respectively, the n⁺ doped drain region of n-channel LDMOStransistors, the p⁺ doped source region of p-channel LDMOS transistors,the n⁺ doped drain region of n-channel MOS transistors and the p⁺ dopedemitter region of the PNP transistors.

In the case of an n-channel LDMOS transistor, the presence of thisauxiliary n-doped region, obtained by implanting phosphorus through thedrain area, increases the breakdown voltage because the field intensitybetween the drain and the gate is reduced while obtaining a reductiontoo of the conducting resistance (R_(on)) of the transistor, which isextremely advantageous when the LDMOS transistor itself is used as anintegrated power switching device, as it is often the case in thesemixed technology integrated devices.

In the case of a p-channel LDMOS transistor, the same auxiliary n⁻ dopedregion may conveniently constitute a body region which is so formedwithout other specific additional process steps.

The CMOS structures formed by pairs of complementary LDMOS transistors,when provided with such an n-doped region by phosphorus implantation,become capable of operating with a supply voltage of about 20 V withoutrequiring special precautions, such as “field plates”, thus remainingadvantageously compact.

In the case of an n-channel MOS transistor belonging to another type ofCMOS structure, the n-doped region, obtained by phosphorus implantationin the drain area of the transistor, reduces the sensitivity toelectrical stresses due to hot electrons, by acting as a “drainextension” region; this permits to the transistor to withstand a supplyvoltage of about 12 V.

In the case of an isolated collector, vertical PNP bipolar transistor,the additional n-doped region obtained by phosphorus implantationthrough the emitter area of the transistor, permits to improve thetransistor's performance transistors by increasing the charge in thebase region of the transistor and to increase the “punch-through”voltage between emitter and collector.

The parallel ability of the different CMOS structures and vertical PNPtransistors to withstand a specifically increased operating voltagespecifically increased permits to build mixed technology integratedcircuits (i.e. “smart power” devices) with far less pronouncedinterfacing problems among the different types of circuits, withenhanced possibilities of fully exploiting the intrinsic peculiaritiesof the different devices and with a higher degree of reliability.

BRIEF DESCRIPTION OF THE DRAWINGS

The peculiar aspects and advantages of the present invention, willbecome evident through the following detailed description of a preferredembodiment illustrated as a nonlimitative example in the attacheddrawings, wherein:

FIG. 1 is a partial schematic, sectional view of an integrated circuitmade in accordance with the present invention;

FIG. 2 shows equimodal, electric field lines in the overlapping regionbetween the gate and the drain region of an n-channel LDMOS transistorof the prior art, without the additional n-doped region of theinvention, produced by computer simulation;

FIG. 3 shows equimodal electric field lines in the same overlappingregion of the preceding figure, in the case of a transistor providedwith the additional n-doped region in accordance with the presentinvention, produced by computer simulation.

DESCRIPTION OF THE BEST MODE

An hypothetical partial cross section of an integrated “smart power”type integrated device, wherein it is relatively easy to put inevidence, though in a schematic way, the aspects of the invention, isshown in FIG. 1. The depicted cross section does not include VDMOS powertransistors, which may be easily imagined present in a different zone ofthe integrated device from the zone shown in the partial cross sectionof the figure, wherein two different CMOS structures are depicted, afirst structure formed by an n-channel and a p-channel LDMOS transistorand a second structure formed by a p-channel and by an n-channel MOStransistor, and the structure of an isolated collector, vertical PNPbipolar transistor.

The device comprises a p-type silicon substrate 1 on which an epitaxialn-type silicon layer 2 has been grown after doping with arsenic and/orwith boron certain areas defined on the surface of the monocrystallinesilicon substrate 1 in order to form the n⁺ buried layers 3 and thep-type bottom isolations 4. The integrated device further comprises anisolation structure among the different integrated devices which, in thedepicted example, is formed by a field oxide layer 5 grown on thesurface of the silicon 2, after doping with boron predifined predefinedareas on the silicon surface in order to form, in accordance with wellknown techniques, the p-well regions 6 (i.e. top isolations and p-well)as well as regions with a heavier boron doping charge 11, also known asp-field region, while growing the field oxide 5, according to a knowntechnique.

Within active areas destined to the formation of MOS-type devices, gatestructures 12, commonly of doped polycrystalline silicon, are formed.

Typically the n-channel, LDMOS transistor comprises a p-body region 7,produced in the silicon by implanting boron under self-alignmentconditions in the source area extending between the gate 12 and thefield oxide 5 and by successively diffusing the implanted boron untilobtaining the desired diffusion profile of the region 7, the n⁺ sourceand drain junctions 10 and the p⁺ region 9 having a relatively highdoping level formed in the source region for contacting the body region7.

Similarly a p-channel LDMOS transistor comprises a p-doped region 7(having substantially the same profile of the n-channel LDMOS bodyregion), formed in the drain region of the transistor, the p⁺ drain andsource junctions 9 and the n⁺ region 10, formed in the source area inorder to contact an n-body region, the formation of which together withother n-regions in the different integrated structures according to thepresent invention will be described later.

The p-channel MOS transistor forming the second CMOS structure depictedin FIG. 1, comprises, as usual, the source and drain p⁺ junctions 9 anda “back gate” contact, n⁺ region 10, formed in the source zone of thetransistor. Similarly the n-channel MOS transistor comprises the n⁺source and drain junctions 10 and a “back gate” contact, p⁺ region 9,formed in the source zone of the transistor.

The structure of the isolated collector PNP vertical transistorcomprises the collector (C) and emitter (E) contact p⁺ diffusions 9 andthe base (B) n⁺ contact diffusion 10.

In accordance with the present invention, an n-type region 8, doped withphosphorus, extends from the surface of the epitaxial layer respectivelyin the drain area of the n-channel LDMOS transistor extending betweenthe gate electrode and the isolation field oxide, in the source area ofthe p-channel LDMOS transistor extending between the gate electrode andthe isolation field oxide, in the drain area of the n-channel MOStransistor extending between the gate electrode and the adjacentisolation field oxide and in the emitter area of the isolated collectorPNP bipolar transistor defined by the surrounding isolation field oxide,for a depth sufficient to contain at least, respectively, the n⁺ drainjunction of the n-channel LDMOS transistor, the p⁺ source junctions andn⁺ body contact regions of the p-channel LDMOS transistor, the n⁺ drainjunction of the n-channel MOS transistor and the n⁺ emitter junction ofthe PNP transistor.

These n-type regions 8 are made evident in the schematic cross sectiondepicted in FIG. 1 by means of a thick line.

As it will be evident to the skilled technician, the distinct regions 8may be easily formed simultaneously in the indicated zones withoutrequiring critical process steps by simply implanting phosphorus underself-alignment conditions in the indicated areas and by diffusing theimplanted phosphorus before proceeding to the formation of the heavilydoped n⁺ regions obtained by implanting arsenic and diffusing it and ofthe heavily doped p⁺ regions obtained by implanting boron and diffusingit, which are contained within said auxiliary regions 8. In a normalfabrication process the doping level of this additional n-region 8 maybe comprised between 10 ¹³ and 10 ¹⁴ (phosphorus) atoms per cubiccentimeter.

Shown in FIG. 2 are the equimodal electric field lines in theoverlapping region between the drain and the gate of an n-channel LDMOStransistor having a 600 Angstroms (A) thick gate oxide, produced bymeans of computer model simulation for the case of a transistor withoutthe auxiliary n-doped region (8 of FIG. 1) in accordance with thepresent invention and subjected to a 20 V bias. The maximum electricfield intensity is evaluated to be 6×10⁵ V/cm.

Similarly, shown in FIG. 3 are the equimodal electric field lines in thesame overlapping region under identical bias conditions (20 V) of theexample shown in FIG. 2, but wherein the n-channel LDMOS transistor isprovided with the auxiliary n-region, doped with phosphorus at 10 ¹⁴atoms per cubic centimeter, in accordance with the present invention. Asit is easily noted by comparing the FIGS. 2 and 3, in the latter theequimodal electric field lines are more “distended” than those of FIG. 1and the maximum field electric intensity may be evaluated to be 5×10⁵V/cm. This is 17% less than the maximum intensity evaluated in the caseof the transistor of the prior art without the auxialiary auxiliaryphosphorus doped region.

The CMOS structure formed by the complementary LDMOS transistorsprovided with the n-doped region 8 (FIG. 1) in accordance with thepresent invention may funtions functions with a supply voltage of 20 Vand it may be directly interfaced, as a driving device, with VDMOS powertransistors for example, thus eliminating the need for adequate levelshifting circuits. Moreover, an LDMOS transistor structure modifiedaccording to the invention is intrinsically capable of withstandingvoltages in the order of 20 V without requiring the formation of “fieldplates” (according to a known technique for increasing the intrinsicbreakdown voltage of integrated transistors) which inevitably clasheswith compactness requirements of these integrated structures.

Naturally, as it will appear evident to the skilled technician, thecomplementary LDMOS transistors, depicted as forming a CMOS structure inFIG. 1, may themselves be employed as power transistors through anappropriate layout configuration, exploiting also for such applications,the same improved performance in terms of voltage withstanding abilityand reduced resistance (R_(on)), derived by the presence of saidadditional n-region 8, in accordance with the present invention.

Also the electrical performances of the other CMOS structure shown,formed by the pair of complementary MOS transistors, are improvedbecause the n-region 8 formed in the drain region of the n-channeltransistor acts as a drain extension region thus increasing the nominaloperating voltage of the relative CMOS structure.

Another, non-negligeable advantage is obtained also in terms of improvedperformance of the isolated collector, vertical PNP bipolar transistorby providing also this integrated device with the n-region 8 doped withphosphorus enchroaching encroaching in the base region of thetransistor. The consequent increase of the doping level of the baseregion reduces sensitivity to depletion of the base region thusincreasing the punchthrough voltage between emitter and collector. Thispermits also to this integrated component of the “smart power” device tofunction under a relatively high voltage, thus broadening thepossibility of employing this type of transistor which is outstandinglysuited, in respect to other types of transistors, for implementingcircuits with a higher cut-off frequency then that which may be obtainedby means of lateral PNP transistors.

What we claim is:
 1. A monolithically integrated circuit formed in ann-type epitaxial silicon layer grown on a p-type monocrystalline siliconsubstrate and comprising at least a first CMOS structure formed by apair of complementary LDMOS transistors, the first having an n-typechannel and the other a p-type channel, a second CMOS structure formedby a pair of complementary MOS transistors, a first having a p-typechannel and the other an n-type channel, and at least an isolatedcollector, vertical PNP bipolar transistor, characterized by comprising:phosphorus doped n-type silicon regions having the same diffusionprofile which extend from the surface of said epitaxial n-type siliconlayer, respectively in: a drain area region of said n-channel LDMOStransistor defined between a gate electrode of the transistor and anadjacent isolation field oxide, a source area body region of saidp-channel LDMOS transistor defined between a gate electrode of thetransistor and an adjacent isolation field oxide, a drain area region ofsaid n-channel MOS transistor, defined between a gate electrode of thetransistor and an adjacent isolation field oxide, and an emitter areaabase region of said isolated collector, vertical, PNP transistor,defined by a surrounding isolation field oxide, into said epitaxialn-type silicon layer by a depth sufficient to contain, respectively: ann+ drain diffusion of said n-channel LDMOS transistor, a p+ sourcediffusion of said p-channel LDMOS transistor, an n+ drain diffusion ofsaid n-channel MOS transistor, and a p+ emitter diffusion and furtherextending beyond said p+ emitter diffusion into a base region of saidisolated collector, vertical, PNP transistor.
 2. The monolithicallyintegrated circuit as claimed in claim 1 wherein said first and secondLDMOS transistors form a CMOS structure capable of operating a withdriving voltage level of 20 V.
 3. The monolithically integrated circuitas claimed in claim 1 wherein said first and second MOS transistors forma CMOS structure capable of operating with a driving voltage level of 12V.
 4. An integrated circuit fabricated in a silicon layer having a firstconductivity type on a substrate having a second conductivity typeopposite that of the first conductivity type, the integrated circuitincluding first and second LDMOS transistors, a MOS transistor, and anisolated collector vertical bipolar transistor, comprising: a drainregion of the first LDMOS transistor having the first conductivity typeand extending from a surface of the silicon layer to a sufficient depthto contain a shallower more heavily doped region of the firstconductivity type formed in the drain region; a body region of thesecond LDMOS transistor formed in a region of the silicon layer doped tohave the second conductivity type, the body region having the firstconductivity type and extending from the surface of the silicon layer toa sufficient depth to contain a shallower more heavily doped region ofthe second conductivity type formed in the body region; a drain regionof the MOS transistor formed in a region of the silicon layer doped tohave the second conductivity type, the drain region having the firstconductivity type and extending from the surface of the silicon layer toa sufficient depth to contain a shallower more heavily doped region ofthe first conductivity type formed in the drain region; and a baseregion of the isolated collector vertical bipolar transistor, the baseregion including a first region of the first conductivity type extendingfrom the surface of the silicon layer to a depth greater than a depth ofa shallower more heavily doped region of the second conductivity typeformed in the first region, and the base region further including asecond region in which the first region is formed, the second regionformed from a portion of the silicon layer that is encompassed by a wellregion of the second conductivity type, the second region extending fromthe surface of the silicon layer to a depth greater than the depth ofthe first region.
 5. The circuit of claim 4 wherein the firstconductivity type is n-type and the second conductivity type is p-type.6. An integrated circuit fabricated in a silicon layer having a firstconductivity type on a substrate having a second conductivity typeopposite that of the first conductivity type, comprising; a first LDMOStransistor having a drain region between a gate electrode of the firstLDMOS transistor and an adjacent isolation field oxide, the drain regionhaving the first conductivity type and extending from a surface of thesilicon layer to a sufficient depth to contain a shallower more heavilydoped region of the first conductivity type; a second LDMOS transistorhaving a body region between a gate electrode of the second LDMOStransistor and an adjacent isolation field oxide, the body region havingthe first conductivity type and extending from the surface of thesilicon layer to a sufficient depth to contain a shallower more heavilydoped region of the second conductivity type; a MOS transistor having adrain region between a gate electrode of the MOS transistor and anadjacent isolation field oxide, the drain region having the firstconductivity type and extending from the surface of the silicon layer toa sufficient depth to contain a shallower more heavily doped region ofthe first conductivity type; and an isolated collector vertical bipolartransistor having a base region surrounded by an isolation field oxide,the base region having a first region of the first conductivity typethat extends from the surface of the silicon layer to a sufficient depthto contain a shallower more heavily doped region of the secondconductivity type and the base region further having a second regionformed from a portion of the silicon layer that is encompassed by a wellregion of the second conductivity type, the second region extending fromthe surface of the silicon layer to a sufficient depth to contain thefirst region.
 7. The circuit of claim 6 wherein the first conductivitytype is n-type and the second conductivity type is p-type.
 8. Thecircuit of claim 6 wherein the silicon layer is an n-type epitaxiallayer.
 9. An integrated circuit, comprising: a p-type substrate; ann-type epitaxial silicon layer overlying the p-type substrate, then-type epitaxial silicon layer having a surface; an n-channel LDMOStransistor having a drain region between a gate electrode of then-channel LDMOS transistor and an adjacent isolation field oxide, thedrain region having an n ⁻ type doping profile extending from thesurface of the n-type epitaxial silicon layer to a sufficient depth tocontain a shallower more heavily doped region which has an n+ typedoping profile; a p-channel LDMOS transistor having a body regionbetween a gate electrode of the p-channel LDMOS transistor and anadjacent isolation field oxide, the body region having an n ⁻ typedoping profile extending from the surface of the n-type epitaxialsilicon layer to a sufficient depth to contain a shallower more heavilydoped region which has a p+ type doping profile; an n-channel MOStransistor having a drain region between a gate electrode of then-channel MOS transistor and an adjacent isolation field oxide, thedrain region having an n ⁻ type doping profile extending from thesurface of the n-type epitaxial silicon layer to a sufficient depth tocontain a shallower more heavily doped region which has an n+ typedoping profile; a p-channel MOS transistor; and an isolated collector,vertical PNP transistor having a base region surrounded by an isolationfield oxide, the base region having a first region with an n ⁻ typedoping profile that extends from the surface of the n-type epitaxialsilicon layer to a sufficient depth to contain a shallower more heavilydoped p+ emitter region, and the base region further having a secondregion formed from a portion of the n-type epitaxial silicon layer thatis encompassed by a p-well region, the second region extending from thesurface of the n-type epitaxial silicon layer to a sufficient depth tocontain the first region.
 10. An integrated circuit, comprising: ap-type substrate; an n-type epitaxial silicon layer overlying the p-typesubstrate, the n-type epitaxial silicon layer having a surface; ann-channel LDMOS transistor, including a drain region formed in then-type epitaxial layer between a gate electrode of the n-channel LDMOStransistor and an adjacent isolation field oxide, the drain regionhaving a diffused n ⁻ doping profile extending from the surface of then-type epitaxial silicon layer to a sufficient depth to contain ashallower more heavily doped region that has an n+ type doping profile,and a body region formed in the n-type epitaxial layer between the gateelectrode of the n-channel LDMOS transistor and an adjacent isolationfield oxide, the body region having a p-type doping profile extendingfrom the surface of the n-type epitaxial silicon layer to a sufficientdepth to contain a shallower more heavily doped n+ type source region; ap-channel LDMOS transistor, including a drain region between a gateelectrode of the p-channel LDMOS transistor and an adjacent isolationfield oxide, the drain region having a p-type doping profile extendingfrom the surface of the n-type epitaxial silicon layer to a sufficientdepth to contain a shallower more heavily doped region which has a p+type doping profile, and a body region between the gate electrode of thep-channel LDMOS transistor and an adjacent isolation field oxide, thebody region having a diffused n ⁻ doping profile extending from thesurface of the n-type epitaxial silicon layer to a sufficient depth tocontain a shallower more heavily doped p+ type source region; ann-channel MOS transistor, including a drain region between a gateelectrode of the n-channel MOS transistor and an adjacent isolationfield oxide, the drain region having a diffused n ⁻ doping profileextending from the surface of the n-type epitaxial silicon layer to asufficient depth to contain a shallower more heavily doped region thathas an n+ type doping profile, and an n+ type source region formed in ap-well region between the gate electrode of the n-channel MOS transistorand an adjacent isolation field oxide; a p-channel MOS transistor,including a p+ type drain region formed in the n-type epitaxial layerbetween a gate electrode of the p-channel MOS transistor and an adjacentisolation field oxide, and a p+ type source region formed in the n-typeepitaxial layer between the gate electrode of the p-channel MOStransistor and an adjacent isolation field oxide; and an isolatedcollector vertical PNP transistor, including a base region surrounded byan isolation field oxide and including a first region with a diffused n⁻ doping profile that extends from the surface of the n-type epitaxialsilicon layer to a sufficient depth to contain a shallower more heavilydoped p+ emitter region, the base region further having a second regioncomprising a portion of the n-type epitaxial silicon layer that isencompassed in a p-well region, the second region extending from thesurface of the n-type epitaxial silicon layer to a sufficient depth tocontain the first region, and an n+ type region formed between anisolation field oxide and the isolation field oxide surrounding the baseregion to extend from the surface of the n-type epitaxial silicon layerinto the second region; and an isolated collector region extending intothe p-well encompassing the second region.
 11. An integrated circuitfabricated in an n-type silicon layer on a p-type substrate, comprising:an n-channel LDMOS transistor including an n+ source region contacthaving a depth and a p-type body region in the silicon layer surroundingand having a depth greater than the depth of the n+ source regioncontact, a gate capacitively coupled to the p-type body region near thesource region contact to create a voltage-controlled conduction channelin the body region, and an n+ drain region contact having a depth and adiffused n ⁻ lightly-doped drain region in the silicon layer surroundingand having a depth greater than the depth of the n+ drain regioncontact, the n+ drain region contact positioned on the opposite side ofthe channel as the n+ source region contact; and a p-channel LDMOStransistor including a p+ source region contact having a depth and adiffused n ⁻ lightly-doped body region in a p-doped portion of then-type silicon layer surrounding and having a depth greater than thedepth of the p+ source region contact, a gate capacitively coupled tothe body region near the source region contact to create avoltage-controlled conduction channel in the body region, and a p+ drainregion contact having a depth and a p-type lightly-doped drain region inthe p-doped portion of the silicon layer surrounding and having a depthgreater than the depth of the p+ drain region contact, the p+ drainregion contact positioned on the opposite side of the channel as the p+source region contact.
 12. The circuit of claim 11 wherein the p-typebody region of the n-channel LDMOS transistor has a diffusion profilewhich is the same as that of the p-type lightly doped drain region ofthe p-channel LDMOS transistor.
 13. The circuit of claim 11 wherein then-type lightly doped drain region of the n-channel LDMOS transistor hasa diffusion profile which is the same as that of the n-type body regionof the p-channel LDMOS transistor.
 14. The circuit of claim 11 whereinthe p-type body region of the n-channel LDMOS transistor has a diffusionprofile which is the same as that of the p-type lightly doped drainregion of the p-channel LDMOS transistor and the n-type lightly dopeddrain region of the n-channel LDMOS transistor has a diffusion profilewhich is the same as that of the n-type body region of the p-channelLDMOS transistor.
 15. A method for fabricating an integrated circuit,comprising the steps of: providing a semiconductor substrate having afirst conductivity type; forming on the substrate a silicon layer havinga second conductivity type; forming in the silicon layer a first regionof the second conductivity type, a second region of the firstconductivity type adjacent the first region, a third region of the firstconductivity type isolated by an isolation region from the secondregion, and forming a fourth region of the second conductivity type in aportion of first-conductivity type formed in the silicon layer;diffusing simultaneously into each of the first, second, third andfourth regions an impurity of the second conductivity type to form ineach of the respective regions a diffused region, each diffused regionhaving the same dopant concentration and depth; and diffusing into thediffused regions an additional dopant of a higher concentration to adepth more shallow than the depth of the diffused regions to form a morehighly doped region in each of the diffused regions.
 16. The method ofclaim 15, further including the steps of forming in the first, second,third, and fourth regions, first and second LDMOS transistors, a MOStransistor, and an isolated collector vertical bipolar transistor,respectively.
 17. The method of claim 15 wherein the first conductivitytype is p-type and the second conductivity is n-type.
 18. The method ofclaim 15 wherein the silicon layer is an epitaxial n-type silicon layer.19. The method of claim 15 wherein the step of diffusing simultaneouslyincludes the step of forming diffused regions having a doping density of10 ¹³ to 10 ¹⁴ phosphorous atoms per cubic centimeter.